A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.
参考文献
| [1] | Kawahara T,Kobayashi T,Jyouno Y.Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories.IEEE J Solid-State Circuits,1996,31(11):1590 |
| [2] | Dickson J F.On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique.IEEE J Solid-State Circuits,1976,11(3):374 |
| [3] | Shin J,Chung I Y,Park Y J.A new charge pump without degradation in threshold voltage due to body effect.IEEE J Solid-State Circuits,2000,35(8):1227 |
| [4] | Racape E,Daga J M.A PMOS-switch based charge pump,allowing low cost implementation on a CMOS standard process.ESSCIRC,2005:77 |
| [5] | Ker M D,Chen S L,Tsa C S.Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes.IEEE J Solid-State Circuits,2006,41(5):1100 |
| [6] | Ker M D,Chen S L.On-chip high-voltage charge pump circuit in standard CMOS processes with polysilicon diodes.ASSCC,2005:157 |
- 下载量()
- 访问量()
- 您的评分：
-
10%
-
20%
-
30%
-
40%
-
50%