This paper proposes a new low power structure to improve the trade-off between the bandwidth and the power consumption of a programmable gain amplifier (PGA).The PGA consists of three-stage amplifiers,which includes a variable gain amplifier and DC offset cancellation circuits.The cutoff frequency of the DC offset cancellation circuits can be changed from 4 to 80 kHz.The chip was fabricated in 0.13 μm CMOS technology.Measurement results showed that the gain of the PGA can be programmed from -5 to 60 dB.At the gain setting of 60 dB,the bandwidth can be tuned from 1 to 10 MHz,while the power consumption can be programmed from 850 μA to 3.2 mA at a supply voltage of 1.2 V.Its in-band OIP3 result is at 14 dBm.
参考文献
| [1] | Giannini V,Nuzzo P,Soens C,et al.A 2 mm2 0.1-to-5 GHz SDR receiver in 45 nm digital CMOS.IEEE ISSCC,2009,1:408 |
| [2] | Giannini V,Craninckx J,D'Amico S,et al.Flexible baseband analog circuits for software-defined radio front-ends.IEEE J Solid-State Circuits,2007,42(7):1501 |
| [3] | Mashhour A,Domino W,Beamish N.On the direct conversion receiver-a tutorial.Microwave J,2001,44(6):114 |
| [4] | Razavi B.RF microelectronics.New Jersey:Prentice Hall,1998 |
| [5] | Tsou S C.A low-power CMOS linear-in-decibel variable gain amplifier with programmable bandwidth and stable group delay.IEEE Trans Circuits Syst Ⅱ,2006,53(12):1436 |
| [6] | Giannini V,Craninckx J.Baseband analog circuits for software defined radio.Netherlands:Springer,2008 |
| [7] | Razavi B.Design considerations for direct-conversion receivers.IEEE Trans Circuits Syst Ⅱ,1997,44(6):428 |
| [8] | Razavi B.Design of analog CMOS integrated circuits.Princeton:McGraw Hill,2000 |
| [9] | Elmala M,Carlton B,Bishop R,et al.A 1.4 V,13.5 mW,10/100 MHz 6th order elliptic filter/VGA with DC-offset correction in 90 nm CMOS.IEEE RFIC,2005:189 |
| [10] | Wu C P,Tuao H W.A 110 MHz 84 dB CMOS programmable gain amplifier with RSSI.IEEE RFIC,2003:639 |
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