参考文献
| [1] | Cai X B,Li F L,Zhang C,et al.A 12 bit 100 MS/s pipelined analog to digital converter without calibration.Journal of Semiconductors,2010,31(11):100 |
| [2] | Ali A,Morgan A,Dillon C,et al.A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration.IEEE J Solid-State Circuits,2010,45(12):2602 |
| [3] | Payne R,Corsi M,Smith D,et al.A 16-bit 100 to 160 MS/s SiGe BiCMOS pipelined ADC with 100 dBFS SFDR.IEEE J SolidState Circuits,2010,45(12):2613 |
| [4] | Zhou L R,Luo L,Ye F,et al.A 12 bit 100 MS/s pipelined ADC with digital background calibration.Journal of Semiconductors,2010,31(11):109 |
| [5] | Peter B,Franz K,Claus K,et al.A 14 b 100 MS/s digitally selfcalibrated pipelined ADC in 0.13 μm CMOS.ISSCC Dig Tech Papers,2006:224 |
| [6] | Murrnann B,Boser B.A 12-b 75 MS/s pipelined ADC using open-loop residue amplifier.ISSCC Dig Tech Papers,2003:330 |
| [7] | Li J,Moon U.Background calibration techniques for multi-stage pipelined ADC's with digital redundancy.IEEE Trans Circuits Syst Ⅱ,2003,50(9):531 |
| [8] | Sepke T,Fiorenza J K,Sodini C G,et al.Comparatorbased switched-capacitor circuits for scaled CMOS technologies.ISSCC Dig Tech Papers,2006:220 |
| [9] | Brooks L,Lee H S.A zero-crossing based 8-bit 200 MS/s pipelined ADC.IEEE J Solid-State Circuits,2007,42(12):2677 |
| [10] | Buchanan J E.Bucket brigade analog-to-digital converter.US Patent,No.4072938,1978 |
| [11] | Berglund C N.Analog performance limitations of charge transfer dynamic shift registers.IEEE J Solid-State Circuits,1971,6(6):391 |
| [12] | Anthony M,Kohler E,Kurtze J,et al.A process-scalable lowpower charge-domain 13-bit pipeline ADC.Symposium on VLSI Circuits,Dig Tech Papers,2008:222 |
| [13] | Frey W.Bucket-brigade device with improved charge transfer.IET Electron Lett,1973,9(25):588 |
| [14] | Anthony M,Kurtze J.Charge domain pipelined analog to digital converter.US Patent,No.7570192,2009 |
| [15] | Yoshioka M,Kudo M,Gotoh K,et al.A 10 b 125 MS/s 40 mW pipelined ADC in 0.18 μm CMOS.ISSCC Dig Tech Papers,2005:282 |
| [16] | Pratap N S,Ashish K,Chandrajit D,et al.20 mW,125 Msps,10 bit pipelined ADC in 65 nm standard digital CMOS process.IEEE CICC Dig Tech Papers,2007:189 |
| [17] | Cheol C H,Ju K Y,Joo K W,et al.A 10 b 120 MS/s 108 mW 0.18 μm CMOS ADC with a PVT-insensitive current reference.Analog Integrated Circuits and Signal Processing,2009,61(58):115 |
| [18] | Lee K H,Lee S W,Kim Y J,et al.Ten-bit 100 MS/s 24.2 mW 0.8 mm2 0.18 μm CMOS pipeline ADC based on maximal circuit sharing schemes.Electron Lett,2009,45(25):1296 |
| [19] | Shin C S,Ahn G C.A 10-bit 100-MS/s dual-channel pipelined ADC using dynamic memory effect cancellation technique.IEEE Trans Circuits Syst Ⅱ,2011,58(5):274 |
上一张
下一张
上一张
下一张
计量
- 下载量()
- 访问量()
文章评分
- 您的评分：
-
10%
-
20%
-
30%
-
40%
-
50%