参考文献
[1] | Lee Y,Seok M,Hanson S,et al.Standby power reduction techniques for ultra-low power processors.IEEE ESSCIRC,2008:186 |
[2] | Kumar A,Qin H,Ishwar P,et al.Fundamental bounds on power reduction during data-retention in standby SRAM.IEEE International Symposium on Circuits and System,2007:1867 |
[3] | Hamzaoglu F,Zhang K,Wang Y,et al.A 3.8 GHz 153 Mb SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal gate CMOS technology.IEEE J SolidState Circuits,2009,44(1):148 |
[4] | Lai F,Lee C.On-chip voltage down converter to improve SRAM read/write margin and static power for sub-nano CMOS technology.IEEE J Solid-State Circuits,2007,42(9):2061 |
[5] | Wang Y,Bhattacharya U,Hamzaoglu F,et al.A 4.0 GHz 291 Mb voltage-scalable SRAM design in a 32 nm high-k + metal-gate CMOS technology with integrated power management.IEEE J Solid-State Circuits,2010,45(1):103 |
[6] | Yamaoka M,Kawahara T.Operating-margin-improved SRAM with columm-at-a-time body-bias control technique.IEEE ESSCIRC Dig,2007:396 |
[7] | Yamaoka M,Shinozaki Y,Maeda N,et al.A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring processvariation immunity and low-leakage-active mode for mobilephone application processor.IEEE J Solid-State Circuits,2005,40(1):186 |
[8] | Lakshminarayanan S,Joung J,Narasimhan G,et al.Standby power reduction and SRAM cell optimization for 65 nm technology.IEEE International Symposium on Quality Electronic Design,2009:471 |
[9] | Maeda N,Komatsu S,Morimoto M,et al.A 0.41 μA standby leakage 32 kb embedded SRAM with low-voltage resumestandby utilizing all digital current comparator in 28 nm HKMG CMOS.IEEE VLSI Circuits Symp Dig,2012:58 |
[10] | Hsu P K,Tang Y,Tao D,et al.A SRAM cell array with adaptive leakage reduction scheme for data retention in 28 nm high-k metal-gate CMOS.IEEE VLSI Circuits Symp Dig,2012:62 |
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