参考文献
| [1] | Alpman E,Lakdawala H,Carley L R,et al.A 1.1 V 50 mW 2.5 GS/s 7 b time-interleaved C-2C SAR ADC in 45 nm LP digital CMOS.IEEE ISSCC Dig Tech Papers,2009:65 |
| [2] | Van Elzakker M,van Tuijl E,Geraedts P,et al.A 1.9 μW 4.4 fJ/conversion-step 10 b 1 MS/s charge-redistribution ADC.IEEE ISSCC Dig Tech Papers,2008:244 |
| [3] | Wei H G,Chan C H,Chio U F,et al.An 8-b 400-MS/s 2-b-percycle SAR ADC with resistive DAC.IEEE J Solid-State Circuits,2012,47(11):2763 |
| [4] | Chen S W M,Brodersen R W.A 6 b 600 MS/s 5.3 mW asynchronous ADC in 0.13μm CMOS.IEEE ISSCC Dig Tech Papers,2006:574 |
| [5] | Razavi B.Principles of data conversion system design.New York:Wiley-IEEE Press,1995 |
| [6] | Lin Y,Chang S,Liu Y,et al.A 5 b 800 MS/s 2 mW asynchronous binary-search ADC in 65 nm CMOS.IEEE ISSCC Dig Tech Papers,2009:80 |
| [7] | Agnes A,Bonizzoni E,Malcovati P,et al.A 9.4-ENOB 1 V 3.8 μW 100 kS/s SAR ADC with time-domain comparator.IEEE International Solid-State Circuits Conference (ISSCC),2008:246 |
| [8] | Lin Y Z,Chang S J,Liu Y T,et al.An asynchronous binarysearch ADC architecture with a reduced comparator count.IEEE Trans Circuits Syst Ⅰ,2010,57(8):1829 |
| [9] | Kobenge S B.Circuit techniques for low-voltage low-power successive approximation register analog-to-digital converter.PhD Thesis,Tsinghua University,2010 |
| [10] | Gustavsson M,Wikner J J,Tan N N.CMOS data converters for communications.Boston:Kluwer Academic Publishers,2000 |
| [11] | Colleran W T.A 10-bit 100-MS/s A/D converter using folding,interpolating,and analog encoding.PhD Thesis,University of California,Los Angeles,CA,1993 |
| [12] | Pan H,Segami M,Choi M,et al.A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR.IEEE J SolidState Circuits,2000,35(12):1769 |
| [13] | Kobenge S B,Yang H.A novel low power time-mode comparator for successive approximation register ADC.IEICE Electronics Express,2009,6(16):1155 |
| [14] | Anderson T.Optimum control logic for successive approximation analog-to-digital converters.Deep Space Network Progress Report,1972,13:168 |
| [15] | Ginsburg B P.Energy-efficient analog-to-digital conversion for ultra-wideband radio.PhD Thesis,MIT,2007:138 |
| [16] | Liu W,Huang P,Chiu Y.A 12-bit,45-MS/s,3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration.IEEE J Solid-State Circuits,2011,46(11):2661 |
| [17] | Taillefer C.Analog-to-digital conversion via time-mode signal processing.PhD Thesis,McGill University,2007 |
| [18] | Cao Z,Yan S,Li Y.A 32 mW 1.25 GS/s 6 b 2 b/step SAR ADC in 0.13μm CMOS.IEEE J Solid-State Circuits,2009,44(3):862 |
| [19] | Fan Hua,Wei Qi,Kebenge Sekedi Bomeh,et al.An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-SFDR.Journal of Semiconductors,2010,31 (9):095011 |
| [20] | Liu Liyuan,Li Dongmei,Chen Liangdong,et al.A low power 8-bit successive approximation register A/D for a wireless body sensor node.Journal of Semiconductors,2010,31 (6):035002 |
| [21] | Ginsburg B P,Chandrakasan A P.500-MS/s 5-bit ADC in 65nm CMOS with split capacitor array DAC.IEEE J Solid-State Circuits,2007,42(4):739 |
| [22] | Yang J,Naing T L,Brodersen R W.A 1 GS/s 6 bit 6.7 mW successive approximation ADC using asynchronous processing.IEEE J Solid-State Circuits,2010,45(8):1469 |
| [23] | Wong S S,Chio U F,Chan C H,et al.A 4.8-bit ENOB 5-bit 500 MS/s binary-search ADC with minimized number of comparators.IEEE ASSCC,2011:73 |
| [24] | Ali A M A,Dillon C,Sneed R,et al.A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter.IEEE J Solid-State Circuits,2006,41(8):1846 |
上一张
下一张
上一张
下一张
计量
- 下载量()
- 访问量()
文章评分
- 您的评分：
-
10%
-
20%
-
30%
-
40%
-
50%