参考文献
| [1] | Chua T T, Ho S W, Li H Y, et al.3D interconnection process development and integration with low stress TSV.Proceedings 60th IEEE Electronic Components and Technology Conference (ECTC), 2010,2010. |
| [2] | Wu Heng,Tang Zhen'an,Wang Zhu,Cheng Wan,Yu Daquan.Simulation of through via bottom-up copper plating with accelerator for the filling of TSVs[J].半导体学报（英文版）,2013(09):178-182. |
| [3] | Liu Xiaoxian,Zhu Zhangming,Yang Yintang,Wang Fengjuan,Ding Ruixue.Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips[J].半导体学报（英文版）,2014(01):121-128. |
| [4] | Li Hailong,Kang Jin,Liu Yuling,Wang Chenwei,Liu Hong,Gao Jiaojiao.Effect of guanidine hydrochloride on removal rate selectivity and wafer topography modification in barrier CMP[J].半导体学报（英文版）,2014(03):163-168. |
| [5] | Tsai T C, Tsao W C, Lin W, et al.CMP process development for the via-middle 3D TSV applications at 28 nm.Microelectron Eng, 2012, 92:29,2012. |
| [6] | Shapiro M, Interrante M, Andry P, et al.Reliable through silicon vias for 3D silicon applications.IEEE International Interconnect Technology Conference, 2009:63,2009. |
| [7] | Ramaswami S, Director S.Recent advances in TSV processing technology.Silicon Systems Group, July 14, 2010,2010. |
| [8] | Liu Song,Shan Guangbao,Xie Chengmin,Du Xinrong.A transmission line-type electrical model for tapered TSV considering MOS effect and frequency-dependent behavior[J].半导体学报（英文版）,2015(02):92-98. |
| [9] | Wei Zhen,Li Xiaochun,Mao Junfa.An accurate RLGC circuit model for dual tapered TSV structure[J].半导体学报（英文版）,2014(09):136-142. |
| [10] | Gao S, Kwong D L.3D IC integration with TSV current progress and future outlook.Institute of Microelectronics, 2010, 9:1,2010. |
| [11] | Ma Suohui, Wang Shengli, Liu Yuling, et al.Alkaline barrier slurry applied in TSV chemical mechanical polishing.Journal of Semiconductors, 2014, 35(2):026002,2014. |
| [12] | Kitada H, Maeda N, Fujimoto K, et al.Development of low temperature dielectrics down to 150 ℃ for multiple TSVs structure with wafer-on-wafer (WOW) technology.IEEE International Interconnect Technology Conference (IITC), 2010:1,2010. |
| [13] | Seo Y J, Lee W S.Effects of oxidant additives for exact selectivity control of W and Ti CMP process.Microelectron Eng, 2005, 77:132,2005. |
| [14] | Zhao Yingbo, Dong Gang, Yang Yintang.Analysis and optimization of TSV-TSV coupling in three-dimensional integrated circuits.Journal of Semiconductors, 2015, 36(4):045011,2015. |
| [15] | Chen J C, Lau J H, Tzeng P J, et al.Effects of slurry in Cu chemical mechanical polishing (CMP) of TSVs for 3-D IC integration.IEEE Trans Components Packaging & Manufacturing Technology, 2012, 2(6):956,2012. |
| [16] | Chiu Y S, Wang Y L, Liu C P, et al.The application of electrochemical metrologies for investigating chemical mechanical polishing of A1 with a Ti barrier layer.Mater Chem Phys, 2003, 82:444,2003. |
上一张
下一张
上一张
下一张
计量
- 下载量()
- 访问量()
文章评分
- 您的评分：
-
10%
-
20%
-
30%
-
40%
-
50%