半导体学报（英文版）, 2015, 36(11): 34-38. doi: 10.1088/1674-4926/36/11/114003

Simulation and research on a 4T-cell based duplication redundancy SRAM for SEU radiation hardening

Keywords： SRAM

参考文献

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[2]	Li, Tianwen;Yang, Haigang;Cai, Gang;Zhi, Tian;Li, Yue.A CMOS Triple Inter-Locked Latch for SEU Insensitivity Design[J].IEEE Transactions on Nuclear Science,20146(6):3265-3273.
[3]	Calin T.;Nicolaidis M..Upset hardened memory design for submicron CMOS technology[J].IEEE Transactions on Nuclear Science,19966(6):2874-2878.
[4]	Petersen E.L.;Pickel J.C..Rate prediction for single event effects-a critique[J].IEEE Transactions on Nuclear Science,19926(6):1577-1599.

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