半导体学报（英文版）, 2015, 36(5): 163-169. doi: 10.1088/1674-4926/36/5/055012

基金项目: Project supported by the National Natural Science Foundation of China (No.61106027).

A 10-bit 250 MSPS charge-domain pipelined ADC with replica controlled PVT insensitive BCT circuit

Keywords： pipelined analog-to-digital converter

参考文献

[1]	Anthony M;Kohler E;Kurtze J.A process-scalable lowpower charge-domain13-bit pipeline ADC[A].,2008:222.
[2]	Anthony M;Sollner G.Ultra-low-power 500-MSPS12-bit A/D converter using interleaving and CMOS charge-domain technology[A].,2009:1.
[3]	Chen Z H;Yu Z G;Huang S R.A PVT insensitive boosted charge transfer for high speed charge-domain pipelined ADCs[J].IEICE ELECTRONICS EXPRESS,20129(6):565.
[4]	Chen Zhenhai;Huang Songren;Zhang Hong.A 27-mW 10-bit 125-MSPS charge-domain pipelined ADC with PVT insensitive boosted charge transfer[J].Journal of Semiconductors,201334(3):035009.
[5]	Chen Zhenhai;Qian Hongwen;Huang Songren;Zhang Hong;Yu Zongguang.A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling[J].半导体学报（英文版）,2013(06):118-125.
[6]	Yoshioka M;Kudo M;Gotoh K.A10 b125 MS/s 40 mW pipelined ADC in 0.18 μm CMOS[A].,2005:282.
[7]	Pratap N S;Ashish K;Chandrajit D.20 mW,125 Msps,10 bit pipelined ADC in 65 nm standard digital CMOS process[A].,2007:189.
[8]	Shin, C.-S.;Ahn, G.-C..A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique[J].IEEE Transactions on Circuits and Systems, II. Express briefs,20115(5):274-278.

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