为了 Camera Link 摄像机的小型化和集成化，设计并实现了基于 FPGA 的 Camera Link 接口的编码输出功能。输出编码分为3个步骤：首先，完成图像像素数据到 Camera Link PORT 的映射；其次，根据 DS90CR287的数据编码要求对 PORT 数据和同步时钟信号进行编码；最后，通过 FIFO 和并串转换功能模块完成图像数据和时钟编码信号的 LVDS信号输出。使用 ModelSim 软件，对像素时钟为40 MHz 的 BASE 模式进行了仿真，同时在实物实验中，完成了像素时钟为40 MHz 的 FULL 模式的实验，通过以上两方面实验验证了设计的 Camera Link 输出编码方案的正确性和可行性。提出的编码方案稳定可靠，可以应用于不同模式下的 Camera Link 编码输出，具有很高的灵活性和应用价值。
In order to miniaturize and integrate Camera Link camera,an output-encoding function based on Camera Link interface was designed and implemented.The implementation is divided into three steps:firstly,mapping image pixel data to the Camera Link PORT;secondly,encoding the PORT data and synchronous clock signal according to the data coding requirements of DS90CR287;fi-nally,completing the LVDS output which contains the image data and clock signal through FIFO and parallel-to-serial conversion module.The BASE model that the pixel clock is 40 MHz was emulated u-sing ModelSim,at the same time,the FULL model that the pixel clock is 40 MHz was experimented. The experimental results demonstrate the correctness and feasibility of the Camera Link output enco-ding scheme.The proposed coding scheme is stable and reliable,it can be used in different modes, with high flexibility and practicability.
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