研究掺杂Dy~(3+)对SrTiO_3晶界层电容器组织性能的影响.Dy~(3+)的加入,在含量较低时可以降低晶粒的界面能,从而可以促进晶粒的长大;而在含量较高时,会引起较高的形变能,为降低形变能,Dy~(3+)易于在晶界上析出第二相质点,这些第二相质点具有细化晶粒的作用.晶界层电容器的有效相对介电常数是由晶粒的大小、晶界层的介电常数和晶界层厚度所决定的.因此,瓷料的配方和制造工艺必须保证晶粒的生长和形成致密均匀的晶界,才有良好的性能.通过配方的调整,瓷片获得了良好的组织与综合性能:ε=68 000,tgδ=1.86×10~(-2),ρ_(50v)=20 GΩ·cm,V_(B (DC))=620 V·mm~(-1),|ΔC·C~(-1)(-25～125℃)|=7.4%.
This article studied the effect of Dy~(3+)-doping on the properties and microstructure of the SrTiO_3 grain boundary layer semiconductor ceramic capacitors (GBLC). Dy~(3+) adding can reduce the boundary energy and then promote the grain growth when the content of Dy~(3+) is lower. But when the content of Dy~(3+) is higher,the distorted energy is high, and to reduce these energy the second particles of Dy~(3+) is easy to precipitate on the boundary. These particles can refine the GBLC grain. The GBLC dielectric properties are determined by the grain size, the dielectric constant and the thickness of boundary layer. So to get the better properties, the ceramic formula and manufacturing process must guarantee the growth of grains and the formation of compact and homogeneous boundary. By adjusting composition,the ceramic chips have gotten better microstructure and properties:ε= 68 000,tgδ=1.86×10~(-2),ρ_(50 w) =20 GΩ·cm, V_(B(DC))=620 V·mm~(-1), |ΔC·C~(-1) (-25～+125℃)|=7.4%.
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