针对传统数字信号处理器件速度上的瓶颈问题,提出了一种基于FPGA的快速中值滤波器设计方法,阐述了快速中值滤波器的硬件构架设计和寄存器传输级代码的实现,对整个系统进行了仿真,并对结果进行了分析说明.
Focusing on the speed problems of the traditional digital signal devices,a design of fast median filter based on FPGA was proposed in this paper. The hardware architecture of fast median filter and the code realization of register transfer were introduced, the whole system was simulated, and the experiment results was analyzed.
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