介绍了一种表征SOI材料电学性质的手段,并对三种不同顶层硅厚度的SIMOX材料进行测试、提取参数,分析材料制备工艺对性能产生的影响.研究结果表明,标准SIMOX材料通过顶层硅膜氧化、腐蚀等减薄工艺制得的顶层硅厚度小于1200nm的超薄SIMOX材料,其顶层硅与BOX层界面有更多的缺陷,会影响到在顶层硅膜上制得的器件的性能,引起NMOSFET的阈值电压升高、载流子迁移率降低.Pseudo-MOSFET方法能够在晶圆水平上快捷有效地表征超薄SIMOX材料的电学性质.
Pseudo-MOSFET technique for electrical characterization of SOI materials was developed and used to study the SIMOX materials with different top silicon film thickness. Electrical parameters were extracted and the influences of manufacturing processes on the properties of SIMOX materials were evaluated. The experiment results showed that the ultra-thin SIMOX materials, which were prepared from standard SIMOX material though thinning processes(oxidation and etch-back etc.),had more defects than standard ones at the top silicon film/BOX interface that enhanced the carrier scattering and had bad impacts on the devices which were made in the top silicon films. It also proved that the Pseudo-MOS-FET is an efficient characterization technique for ultra-thin SIMOX materials.
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