Fowler-Nordheim隧穿被广泛应用于EEPROM和闪存中的擦除操作.多晶硅到多晶硅的F-N隧穿具有较高的隧穿效率.本论文基于分栅闪存存储器的结构,对于多晶硅/隧穿氧化层/多晶硅非平面结构的F-N隧穿及其引起的氧化层退化进行了研究.相比于平面结构,非平面结构显示出更高的F-N隧穿效率,且隧穿效率还可通过降低氧化层厚度或者增加预热氧化处理的方法进一步提高.较低的F-N隧穿电流密度显示出较慢的隧穿氧化层退化速率.降低氧化层厚度或者增加热氧化处理也可减缓隧穿氧化层的退化.另外,论文还讨论了研究结果对于改善分栅闪存擦除特性以及耐久性的意义.
Fowler-Nordheim(F-N) tunnelling is widely used as the erase mechanism in EEPROM and Flash memories. Poly-to-poly F-N tunnelling has greatly enhanced tunnelling efficiency. In this paper, the F-N tunnelling characteristics of the non-planar poly/tunnel oxide/poly structure are studied in a split-gate flash structure. Compared with the planar structure, the non-planar structure shows evidently improved F-N tunnelling efficiency, which could be further improved by thinner tunnel oxide thickness or a pre-thermal oxidation of tunnel oxide. Higher tunnelling efficiency could reduce the erase voltage of split-gate flash. The degradation under constant F-N tunnelling current is also studied. Normalized to the same tunnel charges, lower F-N current is found to have slower oxide degradation rate. Thinner oxide thickness or a pre-thermal oxidation could also slow down the tunnel oxide degradation. Finally, the research result is useful to improve the erase and endurance performance of split-gate flash memory.
参考文献
[1] | Pavan P.;Bez R. .Flash memory cells-an overview[J].Proceedings of the IEEE,1997(8):1248-1271. |
[2] | Yeh B .Single transistor non-volatile electrically alterable semiconductor memory device[P].U S Patent,1991. |
[3] | Kianian S;Levi A;Lee D;Hu Y W.A novel 3 volts-only,small sector erase,high density flash E2PROM[A].Honolulu,USA,1994:71-72. |
[4] | Mih R.0.18 um modular triple self-aligned embedded split-gate flash memory[A].Honolulu,USA,2000:120-121. |
[5] | Samar K. Saha .Design Considerations for Sub-90-nm Split-Gate Flash-Memory Cells[J].IEEE Transactions on Electron Devices,2007(11):3049-3055. |
[6] | Bhat N.;Apte P.P. .Charge trap generation in LPCVD oxides under high field stressing[J].IEEE Transactions on Electron Devices,1996(4):554-560. |
[7] | Young-Bog Park;Dieter K. Schroder .Degradation of thin tunnel gate oxide under constant fowler-Nordheim current stress for a flash EEPROM[J].IEEE Transactions on Electron Devices,1998(6):1361-1368. |
[8] | Gehring A;Selberherr S .Modeling of tunneling current and gate dielectric reliability for nonvolatile memory devices[J].IEEE Transactions on Devices and Materials Reliability,2004,4(03):306-319. |
[9] | Miki H.;Noguchi M. .Electron and hole traps in SiO/sub 2/ films thermally grown on Si substrates in ultra-dry oxygen[J].IEEE Transactions on Electron Devices,1988(12):2245-2252. |
[10] | Crook D;Domnitei M;Webb M;Bonini J.Evaluation of modern gate oxide technologies to process charging[A].Atlanta,USA,1993:255-261. |
[11] | Wen-Ting Chu;Hao-Hsiung Lin;Chia-Ta Hsieh;Hung-Cheng Sung;Yu-Hsiung Wang;Yung-Tao Lin;Chung S. Wang .Shrinkable Triple Self-Aligned Field-Enhanced Split-Gate Flash Memory[J].IEEE Transactions on Electron Devices,2004(10):1667-1671. |
[12] | Brown W D;Brewer J.Nonvolatile Semiconductor Memory Technology:A Comprehensive Guide to Understanding and Using NVSM Devices[M].New York:IEEE Press,1997:10-14. |
[13] | Kao D B;McVittie J P;Nix W D;Saraswat K C.Twodimensional silicon oxidation experiments and theory[A].Washington,DC:USA,1985:388-391. |
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