为了检验传输过程中数据的可靠性,设计了容错可逆的汉明码电路.提出了一种新型的可逆逻辑门(FVG),并且完成了FVG门等价的量子实现.利用FVG门和现有的容错可逆门,实现了汉明码编码电路和检测电路.以(7,4)汉明码设计为实例,根据量子代价和延迟对其进行性能评估,结果证明该电路比现有电路的性能提高10%~20%,仿真实验结果显示,电路逻辑结构正确,性能可靠.
参考文献
[1] | Landauer R.Irreversibility and heat generation in the computing process[J].IBM J.Res.Develop.,1961,5(2):183-191. |
[2] | Bennett C H.Logical reversibility of computation[J].IBM J.Res.Develop.,1973,17(6):525-532. |
[3] | Haghparast M.Design and implementation of nanometric fault tolerant reversible BCD adder[J].Aust.J.Basic & Appl.Sci.,2011,5(10):896-901. |
[4] | Haphparast M,Mohammad M,Navi K,et al.Optimized reversible multiplier circuit[J].J.Circuit Syst.Comp.,2009,18(2):311-323. |
[5] | Mohammadi M,Eshghi M.On figures of merit in reversible and quantum logic designs[C].Quant.Info.Proc.,2009,8(4):297-318. |
[6] | Islam M S,Begum Z.Reversible logic synthesis of fault tolerant carry skip BCD adder[J].J.of Bangladesh Academy of Sci.,2008,32(2):193-200. |
[7] | Lü Hongjun,Peng Fei,Wu Tianhao,et al.Irreversible logic operation accomplished by quantum reversible logic circuits[J].Chinese Journal of Quantum Electronics(量子电子学报),2009,26(6):668-674 (in Chinese). |
[8] | Haghparast M.Design and implementation of nanometric fault tolerant reversible BCD adder[J].Aust.J.Basic & Appl.Sci.,2011,5(10):896-901. |
[9] | Haghparast M,Dastan F.A novel nanometric fault tolerant reversible divider[J].Int.J.Phys.Sci.,2011,6(24):5671-5681. |
[10] | Akbar E P A,Haghparast M,Navi K.Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology[J].Microelectron.J.,2011,42(8):973-981. |
[11] | Qi Xuemei,Chen Fulong,Zuo Kaizhong,et al.Design of fast fault tolerant reversible signed multiplier[J].Int.J.Phy.Sci.,2012,7(17):2506-2514. |
[12] | Haghparast M,Navi K.Novel reversible fault tolerant error coding and detection circuits[J].Int.J.Quant.Inform.,2011,9(2):723-738. |
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