研究了烧结温度对WO_3系电容-压敏复合陶瓷显微结构、非线性电学性能及介电性能的影响.随着烧结温度从1050 ℃到1200 ℃的升高,WO_3陶瓷的晶粒尺寸增大,压敏电压随之降低.在1150 ℃烧结条件下,掺杂0.8 mol% Y_2O_3 的WO_3 压敏陶瓷样品表现出优良的综合电性能,其非线性系数为3.5,相对介电常数为1.13×10~4.然而,过高的烧结温度,不利于样品的非线性电学性能.WO_3系电容-压敏复合陶瓷较适合的烧结温度为1150 ℃,这是因为,在此温度下最有利于样品的晶界势垒结构的形成.
The effect of sintering temperature on the microstructure, nonlinear electrical behavior, and dielectric properties of the Y_2O_3-doped WO_3 ceramics was studied. The decrease in breakdown voltage directly relates to the grain growth of WO_3 grains when increasing the sintering temperatures from 1050 to 1200 ℃. The capacitor-varistor of WO_3- 0.8 mol% Y_2O_3 composite sintered at 1150 ℃ exhibits the maximal nonlinear coefficient of 3.5 and the highest dielectric constant of 1.13 × 10~4. However, higher sintering temperature than 1150 ℃ is not favorable for the nonlinear electrical behavior of the WO_3 ceramics. The best nonlinear properties of the samples sintered at 1150 ℃ can be explained by the most efficient boundary barrier layer with can be formed sintered at the proper temperature.
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